1. Field of the Invention
The present invention relates to a driving device and related image transmission device of a flat panel display, and more particularly, to a driving device and related image transmission device utilizing a plurality of drivers and an encoding unit to transmit data at the same time.
2. Description of the Prior Art
Liquid crystal display (LCD) devices are flat panel displays characterized by thin appearance, low radiation and low power consumption. LCD devices have gradually replaced traditional cathode ray tube (CRT) displays, and been widely applied in various electronic products such as notebook computers, personal digital assistants (PDAs), flat panel televisions, or mobile phones.
An LCD device usually includes an LCD panel, a timing controller, a gate driver, and a source driver. The timing controller is used for generating image data signals, together with control signals and timing signals for driving the LCD panel. The gate driver is used for generating scan signals for turning on and off the pixel circuits, and the source driver is used for generating driving signals based on the image data signals, the control signals and the timing signals.
For displaying images correctly, various signals are transmitted from the timing controller to the source driver via a transmission interface. Common transmission interfaces used in an LCD device include transistor-transistor logic (TTL) interfaces, reduced swing differential signal (RSDS) interfaces, low voltage differential signal (LVDS) interfaces, and mini low voltage differential signal (mini-LVDS) interfaces, etc.
Please refer to FIG. 1. FIG. 1 is a diagram of an external connection condition of a driving device 10 of a flat panel display according to the prior art. The driving device 10 includes a transmitter TX which has a first output node TXA1 and a second output node TXB1. The transmitter TX further includes two terminal resistors RT1 externally connected, which are coupled between the first output node TXA1 and the second output node TXB1 in series. A common voltage VCOM exists between the first output node TXA1 and the second output node TXB1. When a current I is outputted from the first output node TXA1 by the transmitter TX, the current I flows through a node A, the two terminal resistors RT1, a node B in order, and then back to the second output node TXB1 to form a loop. Similarly, when the current I is outputted from the second output node TXB1 by the transmitter TX, the current I flows through the node B, the two terminal resistors RT1, the node A in order, and then back to the first output node TXA1 to form a loop. The driving device 10 is capable of carrying a data amount of two bits within a clock period due to a voltage level of the node A being different from a voltage level of the node B at the same time.
Please refer to FIG. 2 and FIG. 1. FIG. 2 is a diagram of the voltage level of the node A in FIG. 1. The voltage level of the node A has a center being the common voltage VCOM and an amplitude of vibration being (I×RT1). Thus, the voltage level of the node A can be expressed in equations V(A)=VCOM+(I×RT1) or V(A)=VCOM−(I×RT1).
Please refer to FIG. 3 and FIG. 1. FIG. 3 is a diagram of the voltage level of the node B in FIG. 1. The voltage level of the node B has a center being the common voltage VCOM and an amplitude of vibration being (I×RT1). Thus, the voltage level of the node B can be expressed in equations V(B)=VCOM−(I×RT1) or V(A)=VCOM+(I×RT1). The transmitter TX is capable of carrying a data amount of two bits within a clock period due to the voltage level of the node A being different from the voltage level of the node B at the same time.
Please refer to FIG. 4 and FIG. 1. FIG. 4 is a diagram illustrating an internal current driving manner of the transmitter TX in FIG. 1. The transmitter TX includes a first current source 42, a second current source 44, a first switch SW1, a second switch SW2, a third switch SW3, and a fourth switch SW4. The transmitter TX includes the first output node TXA1 located between the first switch SW1 and the second switch SW2, and the second output node TXB1 located between the third switch SW3 and the fourth switch SW4. The transmitter TX further includes two terminal resistors RT1 externally connected, which are coupled between the first output node TXA1 and the second output node TXB1 in series (please refer to FIG. 1). The first current source 42 is coupled to a supply voltage terminal VCC for providing the current I, and the second current source 44 is coupled to a system ground terminal GND for providing a current having the same magnitude but opposite electrode with the current I. The first switch SW1 is coupled to the first current source 42, and the second switch SW2 is coupled between the first switch SW1 and the second current source 44. The third switch is coupled to the first current source 42 and to the first switch SW1, and the fourth switch SW4 is coupled between the third switch SW3 and the second current source 44. The first switch SW1 and the fourth switch SW4 are controlled by a first control signal SC1, and the second switch SW2 and the third switch SW3 are controlled by a second control signal SC2. The first control signal SC1 and the second control signal SC2 are complementary signals.
Please keep referring to FIG. 4. The first switch SW1 and the fourth switch SW4 are turned on and the second switch SW2 and the third switch SW3 are turned off when the first control signal SC1 is high level and the second control signal SC2 is low level. The supply voltage VCC outputs the current I, and then the current I flows through the first switch SW1 and draws out from the first output node TXA1. The current I flows into the second output node TXB1 through external termination resistors RT1 (please refer to FIG. 1) and then flows through the fourth switch SW4. Finally, the current I flows into the system ground terminal GND to form a current loop. Oppositely, the first switch SW1 and the fourth switch SW4 are turned off and the second switch SW2 and the third switch SW3 are turned on when the first control signal SC1 is low level and the second control signal SC2 is high level. The supply voltage VCC outputs the current I, and then the current I flows through the third switch SW3 and draws out from the second output node TXB1. The current I flows into the first output node TXA1 through external termination resistors RT1 (please refer to FIG. 1) and then flows through the second switch SW2. Finally, the current I flows into the system ground terminal GND to form a current loop.
Common transmission interfaces used in driving chips inside flat panel displays usually adopt transistor-transistor logic (TTL) interfaces, reduced swing differential signal (RSDS) interfaces, low voltage differential signal (LVDS) interfaces, and mini low voltage differential signal (mini-LVDS) interfaces, etc. Disadvantages of the transmission interfaces include causing signal de-skew easily, adjusting setup time/hold time difficultly, raising clock rate/data rate difficultly, and not conforming to demands of high resolution panels. Also, the sizes of LCD panels also grow larger with increasing demands for larger-sized applications. Since the image data signals and the clock signals are transmitted separately, as a result, the prior art LCD devices need more signals lines, which further complicates the circuit layout. Furthermore, setup pins of the driving chips will occupy input pins of the driving chips which causes pin gaps to be smaller, lowers yield rates of factories, and increases costs of panel manufacturing.